1. Field of the Invention
The present invention relates to reconstructing data using an oversampling technique, and more specifically, to selecting the proper phase or samples to reconstruct the data.
2. Description of Related Art
Many of today""s electronic devices, such as digital signal processors, require precise timing for proper operation. Typically, a master clock, generated from a crystal oscillator, supplies a timing signal to clock various components of a circuit or device. A second or slave clock signal is also generated. As these clock signals propagate through the circuit, the signals can become skewed. Clock skew can have adverse effects on the operation of the circuit. For example, when sampling a serial data stream, a skewed clock signal would sample portions of the data stream that are not in phase with the true clock, i.e., the sampling time does not coincide with the corresponding time of the actual data. This can cause inaccurate data being reproduced or recovered. Clock skew can be caused by such factors as the resistance and capacitance (RC) transmission delay variations, device. variations, and-localized loading variations. These can include variations in the length and/or density of the wires carrying the clock signals.
Many solutions have been proposed and used to minimize the effects of clock skew on reproduced data. One such solution is to oversample the serial data stream at a frequency higher than the data rate, using a multi-phase clock signal. Sampling occurs at each phase of the clock. Thus, oversampling provides multiple samples during each data interval. Some samples will be in error, caused by the clock skew, while other samples will be an accurate sample of the data. Proper selection of the samples for each data interval will achieve an accurately recovered data signal. Different schemes for the selection are known, such as disclosed in U.S. Pat. No. 5,905,769, entitled xe2x80x9cSystem and Method for High-Speed Skew-Insensitive Multi-Channel Data Transmissionxe2x80x9d to Lee et al. and U.S. Pat. No. 6,266,799, entitled xe2x80x9cMulti-Phase Data/Clock Recovery Circuitry and Methods for Implementing Samexe2x80x9d to Lee et al., both of which are incorporated by reference in their entirety.
However, these schemes can have fixed thresholds for determining which phase of the clock or data samples is selected. Since both the serial data stream and clock skews vary over time and operation, fixed thresholds may not allow optimal settings for every condition. This problem can reduce the performance of the circuit during these conditions.
Accordingly, in order to overcome the disadvantages discussed above in connection with conventional fixed-threshold techniques, methods are needed for accurately recovering data from oversampling serial data streams.
In accordance with one aspect of the invention, a method and apparatus utilizing an oversampling technique is provided where samples are selected based on detecting data transitions and determining phases or samples corresponding to a majority of the transitions. The majority determination is made using counters having variable thresholds. As a result, phases, and therefore samples, can be correctly selected to accurately recover data for varying conditions.
In accordance with an aspect of the present invention, an open-loop data recovery apparatus and method utilizing an oversampling technique is provided, by which the occurrence of data transitions is counted and a proper sampling clock phase is decided. Counters with variable thresholds are used to monitor the occurrence of phase transitions for a phase selection circuit to determine a preferred phase for recovery of sampled data. The thresholds of the counters are further adjusted in reference with the preferred phase decided by the phase selection circuit. By adjusting the thresholds of the counters, the low pass effect of counters, which can be seen as one digital loop filter, can be optimally determined.
In one embodiment, a data recovery system includes a data sampler that oversamples an incoming serial data stream. The sampling is at a rate controlled by a multi-phase clock having a frequency higher than the data rate. In a first embodiment, the clock is a 12-phase clock having a frequency 2.5 times the data rate. In a second embodiment, the clock is a 20-phase clock having a frequency two times the data rate. Thus, at each data interval, the data sampler outputs a plurality of samples. Further, in accordance with one aspect of the present invention, the phases are divided into groups, with the number of groups equal to the number of samples per data interval or data bit. For example, in the first embodiment, if a data frame has ten data bits, there will be three samples per bit or data interval, resulting in each bit being three-times oversampled and three groups of samples (totaling 12 samples) in a 12-phase clock cycle. The first group can comprise samples corresponding to phases 3, 6, 9 and 12; the second group can comprise samples corresponding to phases 1, 4, 7 and 10; and the third group can comprise samples corresponding to phases 2, 5, 8 and 11. In the second embodiment, if the data frame has ten data bits, there will be four samples per bit, resulting in each bit being four-times oversampled and four groups of samples (i.e., 20 samples) in a 20-phase clock cycle.
Also, the number of samples in each group is equal to the number of data intervals in a clock cycle. Thus, within each group, there is a sample corresponding to each data interval. Therefore, each group contains a sufficient number of samples so that, if aligned, those samples could be used to recover the serial data stream during one clock cycle.
The output of the data sampler is coupled to a phase decision circuit. The phase decision circuit detects data transitions. In one embodiment, an exclusive OR (XOR) operation is performed on each sample and its adjacent and subsequent sample to yield transition values. The last sample in a clock cycle is XOR""d with the first sample from the next clock cycle. These transition values are then divided into groups, with the number of groups equal to the number of multiple phases divided by the number of samples per data bit. For example, in the first embodiment, if a data frame has ten data bits, there will be three samples per bit or data interval, resulting in each bit being three-times oversampled and four groups. In the second embodiment, if the data frame has ten data bits, there will be four samples per bit, resulting in each bit being four-times oversampled and five groups. The grouped transition values are then counted to determine which of the groups of samples or phases correspond to the highest transition count. A count is incremented, in one embodiment, when a result indicates a data transition, and in another embodiment, when either one of two adjacent results indicates a data transition. A counter corresponding to that group is incremented, and the samples of the next clock cycle are processed. Processing continues until one counter reaches a threshold, indicating that a group of samples or phases corresponding to that counter is to be selected. This threshold and selection criteria can be varied, according to different embodiments.
In one embodiment, there are three counters, each counter having two thresholds. Initially, the first threshold is set to the binary value of the second threshold shifted right one bit. For example, if the second threshold is set as 13, which is binary 1101, then the first threshold will be set as 4, which is binary 0100. Selection of a group of samples goes to the first counter that reaches the second threshold before any other counter reaches the first threshold. In other words, the group of samples or phases corresponding to that first counter will be used. When a group of samples is chosen, the counters are cleared, and the first threshold is shifted right one bit (e.g., 0100xe2x86x920010). However, if two counters reach the first threshold before any one counter reaches the second threshold, then a group of samples is selected depending on which counter first reached the first threshold. Once the group is selected, the counters are cleared. If the circuit changes phase (i.e., changes groups of samples) three times in series, the process will be restarted with the first threshold being reset.
The output of the phase decision circuit, which contains information on the group of samples or phases selected, is coupled to a multiplexer circuit. The samples from the data sampler are also input to the multiplexer circuit. Using information from the phase decision circuit, the multiplexer circuit selects the appropriate group of samples from the data sampler and outputs these samples. The output of the multiplexer circuit is the recovered data.